Recently, various electronic appliances, precision instruments, and the like, which utilize embedded software, are widely in use. In a development of the embedded software, a hardware emulator, which simulates an operation of hardware embedding software by using a logical hardware model, has been used to verify operations of the embedded software.
Regarding a simulation collaborating software with hardware, it is important to conduct a verification by appropriately synchronizing simulations respective to the software and the hardware, in order to have consistency between execution timings of a case of operating the software in an actual device and a case of operating the software by using a hardware simulation of the actual device. On the other hand, in order to verify the software at high speed, a technology for suppressing a part of the simulation using the hardware model which part does not influence the operation of the software is presented.
However, an infinite loop exists in the embedded software. When the infinite loop is executed, the simulations of the software and the hardware are synchronized with each other. As a result, there is a problem in which simulation time is consumed. In the above-described conventional technologies, the simulations are conducted even for operations which do not influence the verification of the software. Accordingly, the simulations have not been efficiently conducted.